When a semiconductor device such as a metal-oxide-semiconductor field-effect transistors (MOSFETs) is scaled down through various advanced technology nodes, device packing density and device performance are challenged by device layout and contact configuration. Due to more and more restricted design rule (RDR) limitations in advanced technology nodes, such as 65 nm, 40 nm, and 32 nm and beyond, there are various concerns related to the packing density, processing windows, and circuit performance. In various examples, poly-gate jog structure requires more precise critical dimension (CD) control in fabrication process, which impacts the gate density and packing density, causing chip area increase and design cost increase. In another example, an extra metal layer may be implemented to avoid poly gate jog and be compliant with the design rules. In this case, the chip area increases and the fabrication cost increases as well. Therefore, there is a need for a new integrated circuit structure and layout to address the above issues.